In modern measuring devices, especially in modern digital oscilloscopes, a huge number of periodic measuring portions of a signal to be measured and to be displayed per time unit are acquisitioned. In future digital oscilloscopes about 1,000,000 acquisitions per second are determined. Thus, updating the display in a period of 30 milliseconds leads to about 33,000 acquisitions per update cycle to be handled in a display memory of the oscilloscope.
If 33,000 acquisitions are measured in an update cycle, one single pixel per column of the display can be hit 33,000 times in an update cycle in the worst case. Taking into account this worst case, each memory cell in the display memory assigned to a specific pixel of the display has to store a data of ld(33,000)=16 bits. Thus, in case of a display memory with 1250×800 memory cells, a memory capacity of 16 MBits is necessary. Thus a display memory for 4 displays has a memory capacity of 64 MBits. Using an ASIC for implementing such a display memory results in a comparatively too large amount of the total chip area for memory purpose (for example more than 50% of the total chip area).
For reducing the memory space of a display memory in a semiconductor chip, the display memory in US 2014/0009642 A1 is separated in an internal memory and an external memory realized as flash memory or as optical memory. A digital oscilloscope with such kind of memory is known from WO 2010/025196 A1.
The transfer of sampled values from the internal memory to the external memory is performed, if a value in a memory cell of the internal memory reaches its maximum possible value. The transfer is limited by the bandwidth of the interface between internal and external memory resulting in the following disadvantage. In the case, in which in each column of the display only one single pixel per column is hit very often within an update cycle, a limited bandwidth of the interface results in an additional buffering of high frequency values over a longer period requiring a larger length of the memory cells in the internal memory.
Additionally, the transfer of data over the interface varies over time. In addition to times during which the data transfer pauses, times exist during which too many data to be overflowed in the memory cells of the internal memory, which have to be transferred simultaneously. Accordingly, limited bandwidth of the interface leads to a longer buffering of that data in the internal memory, which has to be enlarged in its capacity for this demand.
Furthermore, the case in which in each column of the display only one single pixel per column is hit very often within an update cycle, which leads to unbalanced data transfer over the time.
What is needed, therefore, is an approach for a device, such as a measurement device, with internal and external memory, and a balancing data transfer over time, between the internal and external memory, such as data transfer between internal and external memory for a display memory of a measurement device.